Digital Logic Design (DLD) Complete Course
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What you'll learn
This course includes
- 25.5 hours of video
- Certificate of completion
- Access on mobile and TV
Course content
1 modules • 126 lessons • 25.5 hours of video
Digital Logic Design (DLD) Complete Course
126 lessons
• 25.5 hours
Digital Logic Design (DLD) Complete Course
126 lessons
• 25.5 hours
- Digital Logic Design Playlist | DLD Playlist | Digital Design By Morris Mano Complete Course 01:53
- Lecture 01 | Decimal to Binary | Decimal to Octal | Decimal to Hexadecimal Numbers 10:59
- Lecture 02 | Decimal Fractions to Binary | Decimal to Hexadecimal | Decimal to Octal 12:19
- Lecture 03 | Unlocking the Infinite | Decimal to Binary Conversion | Fractions to Infinite Binary 07:27
- Conversion of Decimal Fractions into Infinite Binary | Calculator Hacks | Infinite 1010 00:51
- Conversion of Decimal Fractions into Binary Number using Calculator 00:32
- Conversion of Decimal Fraction to Octal Number System | Number Systems Conversion 01:00
- Lecture 04 | Binary to Decimal | Octal to Decimal | Hexadecimal to Decimal | Conversion 07:30
- Lecture 05 | Binary to Decimal Fraction | Hexadecimal to Decimal | Octal to Decimal Fractions | 12:24
- Lecture 06 | Binary to Octal | Binary to Hexadecimal | Binary to Hexadecimal | Octal to Hexadecimal 14:42
- Binary Division with Decimal Point | Binary Division Explained 07:35
- Fill the Counting in the Specified Bases 10:53
- Prob 1.5 Determine the base of the numbers in each case for the following operations to be correct: 03:47
- Problem 1.6 The solutions to the quadratic equation x2 - 11x + 22 = 0 is .. What is the base? 02:58
- Important Quiz on Base - 4 Addition 03:48
- Digital Logic Design| DLD Full Course| Base - 3 Subtraction 05:07
- Lecture 07 | Diminished Radix Complement | (r-1)'s Complement | Finding 1's, 7's & 9's Complement 13:30
- Lecture 08 | Radix Complement | r's Complement | 2's Complement | 8's Complement | 10's Complement 09:48
- Lecture 09 | Complement of Numbers | (r-1)'s , r's ,1's, 2's,7's,8's, 9's,10's,15's,16's Complement 11:25
- Lecture 10 | Subtraction Using 9's and 10's Complement | Subtraction of Using Radix Complement 12:20
- Lecture 11 | Binary Subtraction Using 1's and 2's Complement | Binary Subtraction using Complements 08:48
- Signed Binary Numbers | Signed Magnitude | Signed 1's Complement | Signed 2's Complement 16:40
- Arithmetic Addition and Subtraction on Signed Numbers 15:11
- Practice Problem on Signed Subtraction 05:10
- DLD Lecture 12 | BCD Codes | Problems On BCD Addition 20:53
- DLD Lecture 13 | Decimal Codes | 8421 BCD Code | 2421 Code | Excess - 3 Code | 8421 Code 16:00
- DLD Lecture 14 | Gray Codes | Decimal to Gray Code Conversion | Gray Code to Decimal Conversion 16:39
- Error Detecting Code | Parity Bit Generator | Even Parity | Odd Parity | NAK | ACK 06:00
- ASCII Character Code Explained | How to Read ASCII Table 08:39
- Digital Logic Design | DLD Assignment 01 : : Solution Part 01 | Number System Conversion 29:17
- Lecture 12 | Universal Gates NAND & NOR | Implement any Boolean Expression or Circuit with NAND| NOR 12:29
- Lecture 13 | Universal Gates | Making Any Function with NAND Gates with Complemented Approach 03:18
- Universal Gates | Implementing 𝐹 = (𝐴𝐵+𝐶′)𝐷 + 𝐸𝐹 Using NAND Gates Only 06:04
- Lecture 14 | Boolean Algebra Simplification Rules with Examples | Boolean Expressions Simplification 18:42
- Lecture 15 | Problems on Boolean Algebra | Exercise Problem # 2.4 Digital Design by Morris Mano 09:18
- DLD Lecture #15 | Simplify Any Type of Boolean Algebraic Expression | Solve Boolean Algebra 06:14
- Applications of Logic Gates | 10 Solved Problems 28:19
- Lecture 16 | What are Minterms and Maxterms | Standard vs Canonical Form Explained with Examples 23:14
- Lecture 17 | What is K Map ? | Full Explanation | 3 & 4 Variables K - Map With Solved Examples 36:12
- Prime Implicants and Essential Prime Implicants | Solved Problem 12:23
- Prime Implicants & Essential Prime Implicants Explained with Example | Function Simplification 09:17
- K Map Simplification into POS terms | Maxterms into POS conversion in K Map 07:00
- K MAP For POS Expression Simplification | Example 4-35 Use a K - Map to minimize POS expression: 05:55
- 5 Variable K Map with SOP and POS terms 11:58
- DLD Lecture 18 | K Map with Don't Care Conditions | Book Solved Example 3.8 Morris Mano 10:20
- Conversion of POS Form into SOP Form with Solved Problem 10:46
- Analysis of Combinational Circuits | What Type of Questions Can be Asked in the Analysis Procedure? 22:53
- Design of Combinational Circuits | Design Procedure of BCD to Excess-3 Code Converter 14:48
- Digital Logic Design | Lecture # 20 | Half Adder | Complete Design with Practice Problem 12:41
- Digital Logic Design | Lecture # 21 | Full Adder Explained | Very Important 15:49
- Digital Logic Design | Lecture # 22 | Design Full Adder Using Two Half Adders | Important 09:16
- Digital Logic Design | Lecture # 23 | 4 Bit Parallel Adder | 4 Bit Binary Ripple Carry Adder 13:12
- DLD Lec # 24 | Carry Look Ahead Adder | CLA Adder Complete Derivation 22:40
- Half Subtractor #halfsubtractor 10:36
- Full Subtractor Explained 12:10
- DLD Solution Of Post Mid Quiz | Digital Logic Design | Adders | Propagation Delay | CLA | RCA 21:24
- Implementing P = 4Q + 1 Using 4-Bit Adder | Digital Logic Design Explained | Final Exam Problem 08:02
- Digital Logic Design | 4 - Bit Adder Subtractor Circuit Explained with Exercise Problem # 4.13 21:52
- 4-Bit Adder Subtractor Circuit | Overflow Detection in Signed & Unsigned Numbers 18:22
- Digital Logic Design | Practice Problem on 8 Bit Adder Subtractor 07:27
- Digital Logic Design | Problem on 8 Bit Adder Subtractor | Fill Up the Missing Values in Boxes 10:25
- Digital Logic Design | Derivation of BCD Adder | BCD Adder Truth Table and Circuit Diagram Explained 13:14
- Binary Multiplier | 2 Bit By 2 Bit Binary Multiplier | 2-Bit Multiplier Using Half Adders 10:10
- 4 bit By 3 bit Binary Multiplier | Binary Multiplier | Digital Logic Design 13:10
- Magnitude Comparator || 1- bit , 2-bit & 4-bit Magnitude Comparator 23:50
- Digital Logic Design | Decoders 17:17
- DLD Lecture | Design Full Adder Using a Single 3 x 8 Decoder and Draw its Circuit Diagram 05:03
- DLD Lecture | 2 x 4 Decoder Types Based on the Complements of the Inputs and Outputs 11:56
- BCD to 7-Segment Decoder | Full Concept, Circuit Design & Exam Questions Explained 21:59
- Practice Problem on Decoder | Implementing Two Functions using Two 2 x 4 Decoders | Two Methods 11:53
- Design and Implement Full Adder with 3 x 8 Decoder 09:28
- Encoders | Octal to Binary Encoder | 8 to 3 Encoder Explained 11:10
- 4 x 2 High Priority Encoder 08:33
- 4 x 2 Low Priority Encoder 07:42
- 8 x 3 Low Priority Encoder 04:55
- 4 x 2 Mix Priority Encoder 06:45
- Problem 4.29 Design a four input priority encoder - Morris Mano Digital Design in Urdu | Hindi- 08:24
- Multiplexer Explained | 2x1 MUX & 4x1 MUX | Working, Truth Table, Boolean Expression & Circuit 10:28
- 4 x 1 Multiplexer Exam Question 09:38
- Implementing a 4 Variable Function using 4 x 1 Multiplexer 07:44
- Important Practice Problem on Multiplexers and Decoders 11:16
- Problem 4.32 - Implement the following Boolean Function with Multiplexer- Digital Design by Morris 08:32
- 3 Bit Binary Incrementer on 7 Segment Digital Display | Digital Logic Design 18:00
- SR Latch Explained | NOR & NAND Gate SR Latch with Truth Table & States 26:15
- SR Latch with NAND Gates | Timing Diagram of SR Latch | SR Latch in Sequential Circuits 45:39
- What is SR Latch | Timing Diagram of SR Latch | Sequential Circuits | Fully Explained 11:47
- SR Latch with NOR Gates: Sequential Circuits in Digital Design by Morris Mano 10:37
- Gated SR Latch | SR Latch with Enable or Control Input | Timing Diagram of Gated SR Latch 22:18
- Timing Diagram of SR Latch: Sequential Circuits in Digital Logic Design 05:10
- Gated D Latch in Digital Logic Design 11:37
- Comparison Between SR & D Latch 06:18
- D Flip Flop - Block Diagram, Working,, Characteristics & Excitation Table and State Equation 05:27
- Lecture # 02 | Master Slave D Flip Flop | Sequential Circuits | Digital Logic Design 39:35
- Practice Problem Solved on Master Slave D Flip Flop 11:55
- JK Flip Flop in Sequential Circuits 21:36
- Characteristic and Excitation Table of JK Flip Flop in Sequential Circuits 17:39
- T Flip Flop - Block Diagram, Working, Characteristic and Excitation Table and State Equation 05:45
- Conversion of D Flip Flop into JK Flip Flop | JK Flip Flop Using D Flip-Flop in Sequential Circuits 05:14
- Conversion of D Flip Flop into T Flip Flop 08:33
- Timing Diagram of D Flip Flop and JK Flip flop 11:58
- Timing Diagram of D Flip-Flop, T Flip-Flop, and JK Flip-Flop | Negative-Edge Triggered | Solved 12:14
- Problem # 5.6- A sequential circuit with two D flip-flops A and B, two inputs, x and y; Part-A 12:26
- Problem # 5.6 - A sequential circuit with two D flip-flops A and B, two inputs, x and y; Part-B 06:44
- Problem 5.7 - A sequential circuit has one flip flop Q, two I/p x and y , and o/p S in Urdu | Hindi 06:23
- Problem # 5.8 -Derive the state table and the state diagram of the sequential circuit shown as 05:47
- Problem 5.9 A Sequential Circuit has two JK Flip Flops A & B. Digital Design by Morris Mano, 5th Ed 21:19
- Problem # 5.12- For the following state table , Tabulate the reduced state table and state diagram 10:30
- Problem 5.16- Design a Sequential Circuit with two D Flip Flops A & B, one input x and one output y. 05:31
- Problem 6.6: Design a four‐bit shift register with parallel load using D flip‐flops with control IP 11:25
- Problem 6.7: Draw the logic diagram of a four‐bit register with four D flip‐flops and four 4 × 1 mux 03:16
- Important Problems of Digital Logic Design 02:51
- Pattern Detection 1010 with Overlapping Case Using Moore Model 18:42
- 🎯 Detecting Binary Sequence ‘0101’ using Moore Model | Finite State Machine | FSM 09:12
- Design a Sequential Circuit for 0101 Pattern Detection 32:07
- 4-Bit Synchronous Up/Down Counter Using T Flip-Flops | Complete Solution of Exam Problem 16:42
- Bidirectional Shift Register | Important Problem on Timing Diagram Explained Step-by-Step 12:43
- Designing a 3-Bit Gray Code Counter using T Flip-Flops | Synchronous Sequential Circuit Explained 13:30
- Design a BCD Counter Using a 4-Bit Up Counter with Parallel Load & Building a 0–99 Counter 11:39
- Design a 2-Bit Synchronous Up Counter Using JK Flip-Flops | All Steps Explained 11:54
- Universal Shift Register | Shift Register with Parallel Load | Bidirectional Shift Register 08:15
- Exam Problem on Universal Shift Register | Mode Operations Explained 05:25
- Most Important Problem on Universal Shift Registers | Mode Operations Explained 07:11
- Counter with Unused States | Self Correcting State | Self Correcting Counter | Forced Correct State 21:23
- Design a 3 Bit Synchronous Up Down Counter using T Flip Flops 06:43
- 2 Bit Asynchronous Counter | Ripple Counter | 2 Bit Asynchronous Up Counter using JK Flip Flops 08:40
- BCD Ripple Counter | Mod-10 Asynchronous Counter Design & Timing Diagram of BCD Ripple Counter 31:32
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