VLSI Physical Design Full Course
5.0
(2)
26 learners
What you'll learn
This course includes
- 8.5 hours of video
- Certificate of completion
- Access on mobile and TV
Course content
1 modules • 71 lessons • 8.5 hours of video
VLSI Physical Design Full Course
71 lessons
• 8.5 hours
VLSI Physical Design Full Course
71 lessons
• 8.5 hours
- PD Lec 1 - Introduction to Physical Design | Tutorial | VLSI 03:44
- PD Lec 2 - CMOS Basics part 1 | Tutorial | VLSI | Physical Design 05:43
- PD Lec 3 - CMOS Basics part-2 | Tutorial | VLSI | Physical Design 08:29
- PD Lec 4 - CMOS Basics part-3 | Tutorial | VLSI | Physical Design 07:05
- PD Lec 5 - Logic Gate Conversion | Tutorial | VLSI | Physical Design 07:01
- PD Lec 6 - CMOS basics part 4 | Tutorial | VLSI | Physical Design 07:54
- PD Lec 7 - Physical Design Inputs Overview | Tutorial | VLSI | Physical Design 06:17
- PD Lec 8 - Netlists | PD Inputs part-2 | VLSI | Physical Design 04:37
- PD Lec 9 - Timing Library | libs | PD Inputs part-3 | VLSI | Physical Design 11:03
- PD Lec 10 - LEF File | PD Inputs part-4 | VLSI | Physical Design 06:22
- PD Lec 11 - Constraints File | PD Inputs part-4 | VLSI | Physical Design 13:55
- PD Lec 12 - Technology File | Tech File | PD Inputs part-5 | VLSI | Physical Design 04:07
- PD Lec 13 - DEF File | PD Inputs part-6 | VLSI | Physical Design 09:29
- PD Lec 14- Import Design | Milky Way Library | VLSI | Physical Design 08:58
- PD Lec 15- Floor-planning [part-1] | VLSI | Physical Design 07:21
- PD Lec 16- Floor-planning [part-2] | VLSI | Physical Design 07:01
- PD Lec 17- Floorplanning & IO Placement [part-3] | VLSI | Physical Design 14:31
- PD Lec 18- Macro Placement & Floor-planning [part-4] | VLSI | Physical Design 14:21
- PD Lec 19- Macro Placement Guidelines & Floor-planning [part-5] | VLSI | Physical Design 07:59
- PD Lec 20- Macro Channel Spacing Estimation & Floor-planning [part-6] | VLSI | Physical Design 05:21
- PD Lec 21- Macro Placement Guidelines Floor-planning [part-7] | VLSI | Physical Design 08:48
- PD Lec 22- Blockages and Keep-out Margin | Floor-planning | VLSI | Physical Design 06:32
- PD Lec 23 - Macro placement issues | | Floor-planning | VLSI | Physical Design 05:52
- PD Lec 24 - Power planning and power mesh creation| Floor-planning | VLSI | Physical Design 07:35
- PD Lec 25 - Physical Only Cells | Floor-planning | VLSI | Physical Design 09:24
- PD Lec 26 - Sanity Checks -1 | Floor-planning | VLSI | Physical Design 04:58
- PD Lec 27 - Sanity Checks -2 | Floor-planning | VLSI | Physical Design 07:49
- PD Lec 28 - Sanity Checks -3 | Floor-planning | VLSI | Physical Design 05:40
- PD Lec 29 - Cell Orientation and Flipping | Placement | VLSI | Physical Design 08:44
- PD Lec 30 - Interview Questions | VLSI | Physical Design 05:49
- PD Lec 31 - Introduction to Placement | VLSI | Physical Design 06:15
- PD Lec 32 - Placement of std cells | VLSI | Physical Design 05:20
- PD Lec 33 - Placement and Optimization | VLSI | Physical Design 06:23
- PD Lec 34 - place-opt understanding | VLSI | Physical Design 07:34
- PD Lec 35 - Scan Chain Optimization | VLSI | Physical Design 09:24
- PD Lec 36 - Cell Density of std cells | VLSI | Physical Design 07:16
- PD Lec 37 - Pin Density of std cells | VLSI | Physical Design 05:04
- PD Lec 38 - Global Route Congestion | VLSI | Physical Design 05:42
- PD Lec 39 - CMOS Latch Up | VLSI | Physical Design 09:17
- PD Lec 40 - Well Tap Cell | VLSI | Physical Design 04:32
- PD Lec 42 - SVT LVT HVT Cell variants | VLSI | Physical Design 08:09
- PD Lec 41 - Tie Cell | tie low| tie high | VLSI | Physical Design 05:43
- PD Lec 43 - Timing Fixes in placement | Part-1 | VLSI | Physical Design 07:09
- PD Lec 44 - Timing Fixes in placement | Part-2 | VLSI | Physical Design 11:15
- PD Lec 45 - Spare Cells | Physical Only Cells | VLSI | Physical Design 05:54
- PD Lec 46 - Useful Skew | Timing Fixes in placement | VLSI | Physical Design 06:23
- PD Lec 47 - concurrent clock and data optimization| CCD| Timing | placement | VLSI | Physical Design 06:34
- PD Lec 48-Interview Questions | placement | VLSI | Physical Design 01:09
- PD Lec 49 - Introduction to CTS | Clock Tree Synthesis | VLSI | Physical Design 03:41
- PD Lec 50 Clock Tree Synthesis | CTS | VLSI | Physical Design 07:55
- PD Lec 51 How to balance skew and latency? | CTS | Clock Tree Synthesis | VLSI | Physical Design 08:55
- PD Lec 52 CTS Algorithms | CTS | Clock Tree Synthesis | VLSI | Physical Design 04:00
- PD Lec 53 CTS Constraints | Spec File | Clock Tree Synthesis | VLSI | Physical Design 09:19
- PD Lec 54 CTS Exceptions | Float pin | Stop Pin | Exclude Pin | VLSI | Physical Design 08:34
- PD Lec 55 Power Dissipation in clock tree | Clock gating | CTS | VLSI | Physical Design 04:04
- PD Lec 56 Clock Gating Checks | CGC Paths | CTS | VLSI | Physical Design 10:57
- PD Lec 57 Clock Gate Enable Checks | CGC Paths | CTS | VLSI | Physical Design 06:21
- PD Lec 58 Integrated Clock Gates | ICG | CTS | VLSI | Physical Design 05:46
- PD Lec 59 - Master, Generated and Virtual Clocks | Type of clocks | VLSI | Physical Design 10:48
- PD Lec 60 - What is crosstalk ? | CTS | VLSI | Physical Design 07:24
- PD Lec 61 - Crosstalk fixes and prevention | Shielding | NDR | VLSI | Physical Design 06:06
- PD Lec 62 - CTS Analysis | VLSI | Physical Design 05:17
- PD Lec 63 - Post CTS Optimization | VLSI | Physical Design 06:16
- PD Lec 64 - Skew Groups | CTS | VLSI | Physical Design 08:51
- PD Lec 65 - Introduction to Routing | VLSI | Physical Design 06:48
- PD Lec 66 - Routing Concepts | VLSI | Physical Design 08:20
- PD Lec 67 - Global and Detail Routing | VLSI | Physical Design 10:48
- PD Lec 68 - Spef Extraction | VLSI | Physical Design 12:16
- PD Lec 69 - Routing Algorithms Explained | VLSI | Physical Design 13:08
- PD Lec 70 : Timing ECOs | Demystifying late stage adjustment with Example | VLSI | Physical Design 12:36
- PD Lec 71 | Functional ECOs | Explaining late adjustment with Example | VLSI | Physical Design 06:53
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